課程資訊
課程名稱
高等計算機結構
Advanced Computer Architecture 
開課學期
101-1 
授課對象
電機資訊學院  資訊工程學研究所  
授課教師
楊佳玲 
課號
CSIE5059 
課程識別碼
922 U1470 
班次
 
學分
全/半年
半年 
必/選修
選修 
上課時間
星期一6,7,8(13:20~16:20) 
上課地點
資105 
備註
限修過計算機結構。
總人數上限:40人 
Ceiba 課程網頁
http://ceiba.ntu.edu.tw/1011CSIE5059 
課程簡介影片
 
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課程概述

Computer architecture has evolved — from a world of mainframes, minicomputers, and microprocessors, to a world dominated by microprocessors, and now into a world where microprocessors themselves are encompassing all the complexity of mainframe computers.
 

課程目標
This course focuses on advanced computer architecture design such as deep pipelining, techniques to exploit instruction level parallelism and thread level parallelism, and memory hierarchy management.
Students will acquire the skills of evaluating the performance of alternative design choices in system design.
 
課程要求
 
預期每週課後學習時數
 
Office Hours
 
指定閱讀
 
參考書目
Textbook & Reference Books:
Computer Architecture: A Quantitative Approach. Fifth Edition, John L.
Hennessy and David A. Patterson, Morgan, 2011 
評量方式
(僅供參考)
 
No.
項目
百分比
說明
1. 
Midterm 
30% 
 
2. 
Project #2 
30% 
 
3. 
Project #1 
20% 
 
4. 
Presentation 
5% 
 
5. 
Paper summaries / Discussion 
15% 
 
 
課程進度
週次
日期
單元主題
第0週
** Note **  **** This syllabus is subject to change **** 
第1週
9/10  Course Introduction 
第2週
9/17  Lecture:<br>
Basics of Computer Architecture Design  
第3週
9/24  Lecture:<br>
Memory Hierarchy: Cache management & DRAMs 
第4週
10/01  Lecture:<br>
1. Multiprocessors & Thread-Level Parallelism:Topic (I): Cache Coherency<br>
2. Simulator Tutorial (in Lab 204)

 
第5週
10/08  Lecture:<br>
1. Thread-Level Parallelism <br>
2. Multi-core Architecture 
第6週
10/15  <b>Announce project #1: DRAM management in multi-core</b><br>
<font color=blue> Paper Presentation & Discussion</font> (DRAM management in multi-core)<br>
<UL>
<LI>[陳庚佑] Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. ISCA 2008
<LI>[鄒尚軒] Reducing memory interference in multicore systems via application-aware memory channel partitioning, MICRO 2011
<LI>[游舜志] Balancing DRAM Locality and Parallelism in Shared Memory CMP Systems, HPCA 2012
</UL> 
第7週
10/22  Lecture:<br>
1. Dynamic Instrcution Scheduling <br>
2. Branch Predictor 
第8週
10/29  <font color=blue>Paper Presentation & Discussion</font> (branch predictor)
<UL>
<LI>[簡子翔] An analysis of correlation and predictability: what makes two-level branch predictors work, ISCA 1998
<LI>[鄭人榮] Improving Branch Predictors by Correlating on Data Values, MICRO 1999
<LI>[蔡佩伶] Compiler Controlled Value Prediction using Branch Predictor Based Confidence, MICRO 2000
</UL> 
第9週
11/05  <b>Midterm</b>  
第10週
11/12  <font color=blue>Paper Presentation & Discussion</font> (Prefetch)
<UL>
<LI>[裴 彧] Dynamic Speculative Precomputation, MICRO 2001
<LI>[洪偉書] Spatial memory streaming, ISCA 2006
<LI>[薛德明] Coordinated Control of Multiple Prefetchers in Multi-Core Systems, MICRO 2009
</UL>  
第11週
11/19  Lecture:<br>
1. Heterogenous Computing <br>
2. Low-Power Architecture 
第12週
11/26  <font color=blue>Paper Presentation & Discussion</font> (LLC manegment in multi-core)
<UL>
<LI>[陳培基] Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tile CMP Multiprocessors, ISCA 2005
<LI>[蘇嘉冠] Cooperative Caching for Chip Multiprocessors, ISCA 2006
<LI>[唐 杰] Cloudcache: expaning and shrinking private cache, HPCA 2011
</UL>  
第13週
12/03  <b>Final project proposal due</b><br>
<font color=blue>Paper Presentation & Discussion</font> (on energy-efficient DRAM architecture)
<UL>
<LI>[何建忠] Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency, MICRO 2008
<LI>[邱品筑] Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA 2010
<LI>[林映辰] Adaptive Granularity Memory Systems: A Tradeoff between Storage Efficiency and Throughput, ISCA 2011
</UL>  
第14週
12/10  <font color=blue>Paper Presentation & Discussion</font> (on Heterogenous Computing)
<UL>
<LI>[梁益銓] Many-Thread Aware Prefetching Mechanisms for GPGPU Applications, MICRO 2010
<LI>[李承軒] TAP: A TLP-Aware Cache Management Policy for a CPU-GPU Heterogeneous Architecture, HPCA 2012
<LI>[蕭建偉] Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems, ISCA 2012
</UL>  
第15週
12/17  Lecture:<br>
1. 3D ICs <br>
2. Non-volatile Memory/SSDs 
第16週
12/22 (補課)  <font color=blue>Paper Presentation & Discussion</font> (on NVM)
<UL>
<LI>[張育銘] Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity, ICS ’11
<LI>[黃冠中] Essential roles of exploiting internal parallelism of Flash memory based solid state drives in high speed data processing, HPCA ’11
<LI>[曾柏憲] FIOS: a fair, efficient Flash I/O scheduler, FAST ’12
</UL>  
第17週
12/24  <font color=blue>Paper Presentation & Discussion</font> (on 3D architecture)
<UL>
<LI>[林宗立] An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive High-Density TSV Bandwidth, HPCA '10
<LI>[張志瑋] Efficiently Enabling Conventional Block Sizes for Very Large Die-stacked DRAM Caches, MICRO 2011
<LI>[劉昇龍] A Register-file Approach for Row Buffer Caches in Die-stacked DRAMs, MICRO 2011
</UL>  
第18週
01/07  <b>Final project presentation</b> (you will also be asked to turn in a report soon after the presentation.)